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pz3064a/pz3064d 64 macrocell cpld with enhanced clocking product specification supersedes data of 1999 may 07 1999 jun 16 integrated circuits ic27 data handbook
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 2 1999 jun 16 8532162 21792 features ? industry's first totalcmos ? pld both cmos design and process technologies ? fast zero power (fzp ? ) design technique provides ultra-low power and very high speed ? 3 volt, in-system programmable (isp) using a jtag interface on-chip supervoltage generation isp commands include: enable, erase, program, verify supported by multiple isp programming platforms 4 pin jtag interface (tck, tms, tdi, tdo) jtag commands include: bypass, idcode ? high speed pin-to-pin delays of 7.5ns ? ultra-low static power of less than 100 m a ? dynamic power that is more than 70% lower at 50mhz than competing devices ? 5 v tolerant i/os to support mixed voltage systems ? 100% routable with 100% utilization while all pins and all macrocells are fixed ? deterministic timing model that is extremely simple to use ? up to 12 clocks with programmable polarity at every macrocell ? support for complex asynchronous clocking ? innovative xpla ? architecture combines high speed with extreme flexibility ? 1000 erase/program cycles guaranteed ? 20 years data retention guaranteed ? logic expandable to 37 product terms ? advanced 0.35 m e 2 cmos process ? security bit prevents unauthorized access ? design entry and verification using industry standard and philips cae tools ? reprogrammable using industry standard device programmers ? innovative control term structure provides either sum terms or product terms in each logic block for: programmable 3-state buffer asynchronous macrocell register preset/reset up to 2 asynchronous clocks ? programmable global 3-state pin facilitates `bed of nails' testing without using logic resources ? available in plcc, tqfp, and lfbga packages ? industrial grade operates from 2.7 volts to 3.6 volts table 1. pz3064a/pz3064d features pz3064a/pz3064d usable gates 2000 maximum inputs 68 maximum i/os 64 number of macrocells 64 propagation delay (ns) 7.5 packages 44-pin plcc, 44-pin tqfp, 56-ball lfbga, 100-pin tqfp description the pz3064a/pz3064d cpld (complex programmable logic device) is the second in a family of fast zero power (fzp ? ) cplds from philips semiconductors. these devices combine high speed and zero power in a 64 macrocell cpld. with the fzp ? design technique, the pz3064a/pz3064d offers true pin-to-pin speeds of 7.5ns, while simultaneously delivering power that is less than 100 m a at standby without the need for `turbo bits' or other power down schemes. by replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in plds since the bipolar era) with a cascaded chain of pure cmos gates, the dynamic power is also substantially lower than any competing cpld 70% lower at 50mhz. these devices are the first totalcmos ? plds, as they use both a cmos process technology and the patented full cmos fzp ? design technique. the philips fzp ? cplds introduce the new patented xpla ? (extended programmable logic array) architecture. the xpla ? architecture combines the best features of both pla and pal ? type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. the xpla ? structure in each logic block provides a fast 7.5ns pal ? path with 5 dedicated product terms per output. this pal ? path is joined by an additional pla structure that deploys a pool of 32 product terms to a fully programmable or array that can allocate the pla product terms to any output in the logic block. this combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. the speed with which logic is allocated from the pla array to an output is only 1.5ns, regardless of the number of pla product terms used, which results in worst case t pd 's of only 9.0ns from any pin to any other pin. in addition, logic that is common to multiple outputs can be placed on a single pla product term and shared across multiple outputs via the or array, effectively increasing design density. the pz3064a/pz3064d cplds are supported by industry standard cae tools (cadence, exemplar logic, mentor, orcad, synopsys, synario, viewlogic, minc), using text (abel, vhdl, verilog) and/or schematic entry. design verification uses industry standard simulators for functional and timing simulation. development is supported on personal computer, sparc, and hp platforms. device fitting uses either minc or philips semiconductors-developed tools. the pz3064a/pz3064d cpld is reprogrammable using industry standard device programmers from vendors such as data i/o, bp microsystems, sms, and others. the pz3064a/pz3064d also includes an industrystandard, ieee 1149.1, jtag interface through which insystem programming (isp) and reprogramming of the device are supported. pal is a registered trademark of advanced micro devices, inc.
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 3 ordering information order code description i/os drawing number pz3064as7a44 44-pin plcc, 7.5ns t pd, commercial temperature range, 3.0 to 3.6 volt power supply 32 sot187-2 pz3064as10a44 44-pin plcc, 10ns t pd, commercial temperature range, 3.0 to 3.6 volt power supply 32 sot187-2 pz3064as7bc 44-pin tqfp, 7.5ns t pd, commercial temperature range, 3.0 to 3.6 volt power supply 32 sot376-1 pz3064as10bc 44-pin tqfp, 10ns t pd, commercial temperature range, 3.0 to 3.6 volt power supply 32 sot376-1 pz3064as7ec 56-ball lfbga, 7.5ns t pd, commercial temperature range, 3.0 to 3.6 volt power supply 44 sot5161 pz3064as10ec 56-ball lfbga, 10ns t pd, commercial temperature range, 3.0 to 3.6 volt power supply 44 sot5161 pz3064as7bp 100-pin tqfp, 7.5ns t pd, commercial temperature range, 3.0 to 3.6 volt power supply 64 sot386-1 pz3064as10bp 100-pin tqfp, 10ns t pd, commercial temperature range, 3.0 to 3.6 volt power supply 64 sot386-1 pz3064ds10a44 44-pin plcc, 10ns t pd, industrial temperature range, 2.7 to 3.6 volt power supply 32 sot187-2 pz3064ds12a44 44-pin plcc, 12ns t pd , industrial temperature range, 2.7 to 3.6 volt power supply 32 sot187-2 pz3064ds10bc 44-pin tqfp, 10ns t pd, industrial temperature range, 2.7 to 3.6 volt power supply 32 sot376-1 pz3064ds12bc 44-pin tqfp, 12ns t pd, industrial temperature range, 2.7 to 3.6 volt power supply 32 sot376-1 pz3064ds10ec 56-ball lfbga, 10ns t pd, industrial temperature range, 2.7 to 3.6 volt power supply 44 sot5161 pz3064ds12ec 56-ball lfbga, 12ns t pd, industrial temperature range, 2.7 to 3.6 volt power supply 44 sot5161 pz3064ds10bp 100-pin tqfp, 10ns t pd, industrial temperature range, 2.7 to 3.6 volt power supply 64 sot386-1 PZ3064DS12BP 100-pin tqfp, 12ns t pd, industrial temperature range, 2.7 to 3.6 volt power supply 64 sot386-1 xpla ? architecture figure 1 shows a high level block diagram of a 64 macrocell device implementing the xpla ? architecture. the xpla ? architecture consists of logic blocks that are interconnected by a zero-power interconnect array (zia). the zia is a virtual crosspoint switch. each logic block is essentially a 36v16 device with 36 inputs from the zia and 16 macrocells. each logic block also provides 32 zia feedback paths from the macrocells and i/o pins. from this point of view, this architecture looks like many other cpld architectures. what makes the coolrunner ? family unique is what is inside each logic block and the design technique used to implement these logic blocks. the contents of the logic block will be described next. logic block i/o 36 16 16 36 16 16 mc0 mc1 mc15 i/o mc0 mc1 mc15 sp00439 zia logic block logic block i/o 36 16 16 mc0 mc1 mc15 36 16 16 i/o mc0 mc1 mc15 logic block figure 1. philips xpla cpld architecture
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 4 logic block architecture figure 2 illustrates the logic block architecture. each logic block contains control terms, a pal array, a pla array, and 16 macrocells. the 6 control terms can individually be configured as either sum or product terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. in addition, two of the control terms can be used as clock signals (see macrocell architecture section for details). the pal array consists of a programmable and array with a fixed or array, while the pla array consists of a programmable and array with a programmable or array. the pal array provides a high speed path through the array, while the pla array provides increased product term density. each macrocell has 5 dedicated product terms from the pal array. the pin-to-pin t pd of the pz3064a/pz3064d device through the pal array is 7.5ns. if a macrocell needs more than 5 product terms, it simply gets the additional product terms from the pla array. the pla array consists of 32 product terms, which are available for use by all 16 macrocells. the additional propagation delay incurred by a macrocell using 1 or all 32 pla product terms is just 1.5ns. so the total pin-to-pin t pd for the pz3064a/pz3064d using 6 to 37 product terms is 9.0ns (7.5ns for the pal + 1.5ns for the pla). to 16 macrocells 6 5 control pal array 36 zia inputs pla array (32) sp00435a figure 2. philips xpla logic block architecture
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 5 macrocell architecture figure 3 shows the architecture of the macrocell used in the coolrunner ? pz3064a/pz3064d. the macrocell can be configured as either a d or t type flip-flop or a combinatorial logic function. a d-type flip-flop is generally more useful for implementing state machines and data buffering while a t-type flip-flop is generally more useful in implementing counters. each of these flip-flops can be clocked from any one of six sources. four of the clock sources (clk0, clk1, clk2, clk3) are connected to low-skew, device-wide clock networks designed to preserve the integrity of the clock signal by reducing skew between rising and falling edges. clock 0 (clk0) is designated as a asynchronouso clock and must be driven by an external source. clock 1 (clk1), clock 2 (clk2), and clock 3 (clk3) can be used as asynchronouso clocks that are driven by an external source, or as aasynchronouso clocks that are driven by a macrocell equation. clk0, clk1, clk2 and clk3 can clock the macrocell flip-flops on either the rising edge or the falling edge of the clock signal. the other clock sources are two of the six control terms (ct2 and ct3) provided in each logic block. these clocks can be individually configured as either a product term or sum term equation created from the 36 signals available inside the logic block. the timing for asynchronous and control term clocks is different in that the t co time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the t su time is reduced. please see the app note aunderstanding coolrunner ? clocking optionso for more detail. the six control terms of each logic block are used to control the asynchronous preset/reset of the flip-flops and the enable/disable of the output buffers in each macrocell. control terms ct0 and ct1 are used to control the asynchronous preset/reset of the macrocell's flip-flop. note that the power-on reset leaves all macrocells in the azeroo state when power is properly applied, and that the preset/reset feature for each macrocell can also be disabled. control terms ct2 and ct3 can be used as a clock signal to the flip-flops of the macrocells, and as the output enable of the macrocell's output buffer. control terms ct4 and ct5 can be used to control the output enable of the macrocell's output buffer. having four dedicated output enable control terms ensures that the coolrunner ? devices are pci compliant. the output buffers can also be always enabled or always disabled. all coolrunner ? devices also provide a global tri-state (gts) pin, which, when enabled and pulled low, will 3-state all the outputs of the device. this pin is provided to support ain-circuit testingo or abed-of-nails testingo. there are two feedback paths to the zia: one from the macrocell, and one from the i/o pin. the zia feedback path before the output buffer is the macrocell feedback path, while the zia feedback path after the output buffer is the i/o pin feedback path. when the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. when the i/o pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the zia via the i/o feedback path, and the logic implemented in the buried macrocell can be fed back to the zia via the macrocell feedback path. it should be noted that unused inputs or i/os should be properly terminated (see the section on terminations in this data sheet and the application note terminating unused coolrunner ? i/o pins ). init (p or r) d/t q sp00558 clk0 clk0 clk1 clk1 to zia gnd ct0 ct1 gts ct2 ct3 ct4 ct5 v gnd cc gnd pal pla clk2 clk2 clk3 clk3 figure 3. pz3064a/pz3064d macrocell architecture
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 6 simple timing model figure 4 shows the coolrunner ? timing model. the coolrunner ? timing model looks very much like a 22v10 timing model in that there are three main timing parameters, including t pd , t su , and t co . in other competing architectures, the user may be able to fit the design into the cpld, but is not sure whether system timing requirements can be met until after the design has been fit into the device. this is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of x and y routing channels used, etc. in the xpla ? architecture, the user knows up front whether the design will meet system timing requirements. this is due to the simplicity of the timing model. for example, in the pz3064a/pz3064d device, the user knows up front that if a given output uses 5 product terms or less, the t pd = 7.5ns, the t su_pal = 3.5ns, and the t co = 5.5ns. if an output is using 6 to 37 product terms, an additional 1.5ns must be added to the t pd and t su timing parameters to account for the time to propagate through the pla array. totalcmos ? design technique for fast zero power philips is the first to offer a totalcmos ? cpld, both in process technology and design technique. philips employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate implementation allows philips to offer cplds which are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. refer to figure 5 and table 2 showing the i dd vs. frequency of our pz3064a/pz3064d totalcmos ? cpld. (data taken with four up/down loadable 16-bit counters @ 3.3v, 25 c) output pin input pin sp00441 t pd_pal = combinatorial pal only t pd_pla = combinatorial pal + pla output pin input pin dq registered t su_pal = pal only t su_pla = pal + pla registered t co global clock pin figure 4. coolrunner ? timing model typical i dd (ma) frequency (mhz) sp00700 1 20 40 60 80 100 120 140 0 5 10 15 20 25 30 35 40 45 figure 5. i dd vs. frequency @ v dd = 3.3 v, 25 c table 2. i dd vs. frequency v dd = 3.3 v, 25 c frequency (mhz) 0 1 20 40 60 80 100 120 140 typical i dd (ma) 0.03 0.3 4.7 9.4 14.0 18.7 23.2 27.7 32.4
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 7 jtag testing capability jtag is the commonly-used acronym for the boundary scan test (bst) feature defined for integrated circuits by ieee standard 1149.1. this standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of specialized test equipment. the philips pz3064a/pz3064d devices use the jtag interface for insystem programming/reprogramming. although only a subset of the full jtag command set is implemented (see table 5), the devices are fully capable of sitting in a jtag scan chain. the philips pz3064a/pz3064d's jtag interface includes a tap port defined by the ieee 1149.1 jtag specification. as implemented in the philips pz3064a/pz3064d, the tap port includes four of the five pins (refer to table 3) described in the jtag specification: tck, tms, tdi, and tdo. the fifth signal defined by the jtag specification is trst* (test reset). trst* is considered an optional signal, since it is not actually required to perform bst or isp. the philips pz3064a/pz3064d saves an i/o pin for general purpose use by not implementing the optional trst* signal in the jtag interface. instead, the philips pz3064a/pz3064d supports the test reset functionality through the use of its power up reset circuit, which is included in all philips cplds. the pins associated with the tap port should connect to an external pullup resistor to keep the jtag signs from floating when they are not being used. in the philips pz3064a/pz3064d, the four mandatory jtag pins each require a unique, dedicated pin on the device. the devices come from the factory with these i/o pins set to perform jtag functions, but through the software, the final function of these pins can be controlled. if the end application will require the device to be reprogrammed at some future time with isp, then the pins can be left as dedicated jtag functions, which means they are not available for use as general purpose i/o pins. however, unlike competing cplds, the philips pz3064a/pz3064d allow the macrocells associated with these pins to be used as buried logic when the jtag/isp function is enabled. this is the default state for the software, and no action is required to leave these pins enabled for the jtag/isp functions. if, however, jtag/isp is not required in the end application, the software can specify that this function be turned off and that these pins be used as general purpose i/o. because the devices initially have the jtag/isp functions enabled, the jedec file can be downloaded into the device once, after which the jtag/isp pins will become general purpose i/o. this feature is good for manufacturing because the devices can be programmed during test and assembly of the end product and yet still use all of the i/o pins after the programming is done. it eliminates the need for a costly, separate programming step in the manufacturing process. of course, if the jtag/isp function is never required, this feature can be turned off in the software and the device can be programmed with an industry-standard programmer, leaving the pins available for i/o functions. table 4 defines the dedicated pins used by the four mandatory jtag signals for each of the pz3064a/pz3064d package types. table 3. jtag pin description pin name description tck test clock output clock pin to shift the serial data and instructions in and out of the tdi and tdo pins, respectively. tms test mode select serial input pin selects the jtag instruction mode. tms should be driven high during user mode operation. tdi test data input serial input pin for instructions and test data. data is shifted in on the rising edge of tck. tdo test data output serial output pin for instructions and test data. data is shifted out on the falling edge of tck. the signal is tri-stated if data is not being shifted out of the device. table 4. pz3064a/pz3064d jtag pinout by package type device (pin number / macrocell #) device tck tms tdi tdo pz3064a/pz3064d 44-pin plcc 32/c15 13/b15 7/a8 38/d8 44-pin tqfp 26/c15 7/b15 1/a8 32/d8 56-ball lfbga f10/c15 g1/b15 c1/a8 c10/d8 100pin tqfp 62/c15 15/b15 4/a8 73/d8 table 5. pz3064a/pz3064d low-level jtag boundary-scan commands instruction (instruction code) register used description bypass (1111) bypass register places the 1 bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through the selected device to adjacent devices during normal device operation. the bypass instruction can be entered by holding tdi at a constant high value and completing an instruction-scan cycle. idcode (0001) boundary-scan register selects the idcode register and places it between tdi and tdo, allowing the idcode to be serially shifted out of tdo. the idcode instruction permits blind interrogation of the components assembled onto a printed circuit board. thus, in circumstances where the component population may vary, it is possible to determine what components exist in a product.
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 8 3-volt, in-system programming (isp) isp is the ability to reconfigure the logic and functionality of a device, printed circuit board, or complete electronic system before, during, and after its manufacture and shipment to the end customer. isp provides substantial benefits in each of the following areas: ? design faster time-to-market debug partitioning and simplified prototyping printed circuit board reconfiguration during debug better device and board level testing ? manufacturing multi-functional hardware reconfigurability for test eliminates handling of afine lead-pitcho components for programming reduced inventory and manufacturing costs improved quality and reliability ? field support easy remote upgrades and repair support for field configuration, re-configuration, and customization the philips pz3064a/pz3064d allows for 3.3-volt, in-system programming/reprogramming of its eeprom cells via its jtag interface. an on-chip charge pump eliminates the need for externally-provided supervoltages, so that the pz3064a/pz3064d may be easily programmed on the circuit board using only the 3-volt supply required by the device for normal operation. a set of low-level isp basic commands implemented in the pz3064a/pz3064d enable this feature. the isp commands implemented in the philips pz3064a/pz3064d are specified in table 6. please note that an enable command must precede all isp commands unless an enable command has already been given for a preceding isp command. terminations the coolrunner ? pz3064a/pz3064d cplds are totalcmos ? devices. as with other cmos devices, it is important to consider how to properly terminate unused inputs and i/o pins when fabricating a pc board. allowing unused inputs and i/o pins to float can cause the voltage to be in the linear region of the cmos input structures, which can increase the power consumption of the device. the pz3064a/pz3064d cplds have programmable on-chip pull-down resistors on each i/o pin. these pull-downs are automatically activated by the fitter software for all unused i/o pins. note that an i/o macrocell used as buried logic that does not have the i/o pin used for input is considered to be unused, and the pull-down resistors will be turned on. we recommend that any unused i/o pins on the pz3064a/pz3064d device be left unconnected. there are no on-chip pull-down structures associated with the dedicated input pins. philips recommends that any unused dedicated inputs be terminated with external 10k w pull-up resistors. these pins can be directly connected to v cc or gnd, but using the external pull-up resistors maintains maximum design flexibility should one of the unused dedicated inputs be needed due to future design changes. when using the jtag/isp functions, it is also recommended that 10k w pull-up resistors be used on each of the pins associated with the four mandatory jtag signals. letting these signals float can cause the voltage on tms to come close to ground, which could cause the device to enter jtag/isp mode at unspecified times. see the application notes jtag and isp in philips devices and terminating coolrunner ? i/o pins for more information. table 6. low level isp commands instruction (register used) instruction code description enable (isp shift register) 1001 enables the erase, program, and verify commands. erase (isp shift register) 1010 erases the entire eeprom array. program (isp shift register) 1011 programs the data in the isp shift register into the addressed eeprom row. verify (isp shift register) 1100 transfers the data from the addressed row to the isp shift register. the data can then be shifted out and compared with the jedec file. the outputs during this operation can be defined by the user.
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 9 jtag and isp interfacing a number of industry-established methods exist for jtag/isp interfacing with cpld's and other integrated circuits. the philips pz3064a/pz3064d supports the following methods: ? pc parallel port ? workstation or pc serial port ? embedded processor ? automated test equipment ? third party programmers ? high-end isp tools for more details on jtag and isp for the pz3064a/pz3064d, refer to the related application note: jtag and isp in philips cplds . programming specifications symbol parameter min. max. unit dc parameters v ccp v cc supply program/verify 3.0 3.6 v i ccp i cc limit program/verify 200 ma v ih input voltage (high) 2.0 v v il input voltage (low) 0.8 v v sol output voltage (low) 0.5 v v soh output voltage (high) 2.4 v tdo_i ol output current (low) 8 ma tdo_i oh output current (high) 8 ma ac parameters f max tck maximum frequency 10 mhz pwe pulse width erase 100 ms pwp pulse width program 10 ms pwv pulse width verify 10 m s init initialization time 100 m s tms_su tms setup time before tck 10 ns tdi_su tdi setup time before tck 10 ns tms_h tms hold time after tck 25 ns tdi_h tdi hold time after tck 25 ns tdo_co tdo valid after tck 40 ns
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 10 absolute maximum ratings 1 symbol parameter min. max. unit v dd supply voltage 2 0.5 4.6 v v i input voltage 1.2 5.75 v v out output voltage 0.5 v dd +0.5 v i in input current 30 30 ma t j maximum junction temperature 40 150 c t str storage temperature 65 150 c note: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. the chip supply voltage must rise monotonically. operating range product grade temperature voltage commercial 0 to +70 c 3.0 to 3.6 v industrial 40 to +85 c 2.7 to 3.6 v
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 11 dc electrical characteristics for commercial grade devices commercial: 0 c t amb +70 c; 3.0 v v dd 3.6 v symbol parameter test conditions min. max. unit v il input voltage low v dd = 3.0 v 0.8 v v ih input voltage high v dd = 3.6 v 2.0 v v i input clamp voltage 3 v dd = 3.0 v, i in = 18ma 1.2 v v ol output voltage low v dd = 3.0 v, i ol = 12ma 0.5 v v oh output voltage high v dd = 3.0 v, i oh = 12ma 2.4 v i i input leakage current v in = 0 to 5.5 v 10 10 m a i oz 3-stated output leakage current v in = 0 to 5.5 v 10 10 m a i ddq 1 standby current v dd = 3.6 v, t amb = 0 c 80 m a i ddd 1, 2 dynamic current v dd = 3.6 v, t amb = 0 c @ 1mhz 1 ma i ddd 1 , 2 dynamic current v dd = 3.6 v, t amb = 0 c @ 50mhz 25 ma i os short circuit output current 3 1 pin at a time for no longer than 1 second 50 200 ma c in input pin capacitance 3 t amb = 25 c, f = 1mhz 8 pf c clk clock input capacitance 3 t amb = 25 c, f = 1mhz 5 12 pf c i/o i/o pin capacitance 3 t amb = 25 c, f = 1mhz 10 pf notes: 1. see table 2, page 6 for typical values. 2. this parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. inputs are tied to v dd or ground. this parameter guaranteed by design and characterization, not testing. 3. this parameter guaranteed by design and characterization, not by test. ac electrical characteristics 1 for commercial grade devices commercial: 0 c t amb +70 c; 3.0 v v dd 3.6 v symbol parameter 7 10 unit symbol parameter min. max. min. max. unit t pd_pal propagation delay time, input (or feedback node) to output through pal 2 7.5 2 10 ns t pd_pla propagation delay time, input (or feedback node) to output through pal & pla 3 9 3 11.5 ns t co clock to out (global synchronous clock from pin) 2 5.5 2 7 ns t su_pal setup time (from input or feedback node) through pal 3.5 5 ns t su_pla setup time (from input or feedback node) through pal + pla 5 6.5 ns t h hold time 2 0 0 ns t ch clock high time 2 2 2.5 ns t cl clock low time 2 2 2.5 ns t r input rise time 2 100 100 ns t f input fall time 2 100 100 ns f max1 maximum ff toggle rate 2 (1/t ch + t cl ) 250 200 mhz f max2 maximum internal frequency 2 (1/t supal + t cf ) 143 105 mhz f max3 maximum external frequency 2 (1/t supal + t co ) 111 83 mhz t buf output buffer delay time 2 2 2 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 2 5.5 7.5 ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal+pla 2 7 9 ns t cf clock to internal feedback node delay time 2 3.5 4.5 ns t init delay from valid v dd to valid reset 2 20 20 m s t er input to output disable 2, 3 8 9.5 ns t ea input to output valid 2 8 9.5 ns t rp input to register preset 2 9 9.5 ns t rr input to register reset 2 9 9.5 ns notes: 1. specifications measured with one output switching. see figure 6 and table 7 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5pf.
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 12 dc electrical characteristics for industrial grade devices industrial: 40 c t amb +85 c; 2.7 v v dd 3.6 v symbol parameter test conditions min. max. unit v il input voltage low v dd = 2.7 v 0.8 v v ih input voltage high v dd = 3.6 v 2.0 v v i input clamp voltage 3 v dd = 2.7 v, i in = 18ma 1.2 v v ol out p ut voltage low v dd = 2.7 v, i ol = 8ma 0.5 v v ol out ut voltage low v dd = 3.0 v, i ol = 12ma 0.5 v v oh out p ut voltage high v dd = 2.7 v, i oh = 8ma 2.4 v v oh out ut voltage high v dd = 3.0 v, i oh = 12ma 2.4 v i i input leakage current v in = 0 to 5.5 v 10 10 m a i oz 3-stated output leakage current v in = 0 to 5.5 v 10 10 m a i ddq 1 standby current v dd = 3.6 v, t amb = 40 c 100 m a i ddd 1, 2 dynamic current v dd = 3.6 v, t amb = 40 c @ 1mhz 1 ma i ddd 1 , 2 dynamic current v dd = 3.6 v, t amb = 40 c @ 50mhz 25 ma i os short circuit output current 3 1 pin at a time for no longer than 1 second 50 230 ma c in input pin capacitance 3 t amb = 25 c, f = 1mhz 8 pf c clk clock input capacitance 3 t amb = 25 c, f = 1mhz 5 12 pf c i/o i/o pin capacitance 3 t amb = 25 c, f = 1mhz 10 pf notes: 1. see table 2, page 6 for typical values. 2. this parameter measured with a 16bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. inputs are tied to v dd or ground. this parameter guaranteed by design and characterization, not testing. 3. this parameter guaranteed by design and characterization, not by test. ac electrical characteristics 1 for industrial grade devices industrial: 40 c t amb +85 c; 2.7 v v dd 3.6 v symbol parameter 10 12 unit symbol parameter min. max. min. max. unit t pd_pal propagation delay time, input (or feedback node) to output through pal 2 10 2 12 ns t pd_pla propagation delay time, input (or feedback node) to output through pal & pla 3 11.5 3 13.5 ns t co clock to out (global synchronous clock from pin) 2 7 2 8 ns t su_pal setup time (from input or feedback node) through pal 5 6 ns t su_pla setup time (from input or feedback node) through pal + pla 6.5 7.5 ns t h hold time 2 0 0 ns t ch clock high time 3 3.5 ns t cl clock low time 3 3.5 ns t r input rise time 100 100 ns t f input fall time 100 100 ns f max1 maximum ff toggle rate 2 (1/t ch + t cl ) 166 143 mhz f max2 maximum internal frequency 2 (1/t supal + t cf ) 111 95 mhz f max3 maximum external frequency 2 (1/t supal + t co ) 90 77 mhz t buf output buffer delay time 2 2 2 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 2 8 9 ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal+pla 2 9.5 10.5 ns t cf clock to internal feedback node delay time 2 5 5.5 ns t init delay from valid v dd to valid reset 2 20 20 m s t er input to output disable 2, 3 10 12 ns t ea input to output valid 2 10 12 ns t rp input to register preset 2 10 12 ns t rr input to register reset 2 10 12 ns notes: 1. specifications measured with one output switching. see figure 6 and table 7 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5pf.
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 13 switching characteristics the test load circuit and load values for the ac electrical characteristics are illustrated below. v dd v in v out c1 r1 r2 s1 s2 component values r1 390 w r2 390 w c1 35pf measurement s1 s2 t pzh open closed t pzl closed open t p closed closed note: for t phz and t plz c = 5pf sp00623 sp00639 number of outputs switching 1 2 4 8 12 16 v dd = 3.3 v, 25 c 5.3 5.5 5.7 5.9 5.4 5.6 5.8 t pd_pal (ns) 5.2 figure 6. t pd_pal vs. outputs switching table 7. t pd_pal vs. number of outputs switching v dd = 3.3 v, 25 c number of outputs 1 2 4 8 12 16 typical (ns) 5.3 5.3 5.4 5.6 5.7 5.9 voltage waveform 90% 10% 1.5ns 1.5ns +3.0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00368
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 14 pin descriptions pz3064 44-pin plastic leaded chip carrier lcc 6140 7 17 39 29 18 28 pin function 1 in1 2 in3 3v dd 4 i/o-a0/ck3 5 i/o-a2 6 i/o-a5 7 i/o-a8 (tdi) 8 i/o-a11 9 i/o-a12 10 gnd 11 i/o-a13 12 i/o-a15 13 i/o-b15 (tms) 14 i/o-b13 15 v dd pin function 16 i/o-b10 17 i/o-b8 18 i/o-b4 19 i/o-b3 20 i/o-b2 21 i/o-b0/ck2 22 gnd 23 v dd 24 i/o-c0/ck1 25 i/o-c2 26 i/o-c3 27 i/o-c4 28 i/o-c7 29 i/o-c8 30 gnd pin function 31 i/o-c13 32 i/o-c15 (tck) 33 i/o-d15 34 i/o-d13 35 v dd 36 i/o-d12 37 i/o-d11 38 i/o-d8 (tdo) 39 i/o-d7 40 i/o-d2 41 i/o-d0 42 gnd 43 in0-ck0 44 in2-gtsn sp00554 pz3064 44-pin thin quad flat package qfp 44 34 1 11 33 23 12 22 pin function 1 i/o-a8 (tdi) 2 i/o-a11 3 i/o-a12 4 gnd 5 i/o-a13 6 i/o-a15 7 i/o-b15 (tms) 8 i/o-b13 9v dd 10 i/o-b10 11 i/o-b8 12 i/o-b4 13 i/o-b3 14 i/o-b2 15 i/o-b0/ck2 pin function 16 gnd 17 v dd 18 i/o-c0/ck1 19 i/o-c2 20 i/o-c3 21 i/o-c4 22 i/o-c7 23 i/o-c8 24 gnd 25 i/o-c13 26 i/o-c15 (tck) 27 i/o-d15 28 i/o-d13 29 v dd 30 i/o-d12 pin function 31 i/o-d11 32 i/o-d8 (tdo) 33 i/o-d7 34 i/o-d2 35 i/o-d0 36 gnd 37 in0/ck0 38 in2-gtsn 39 in1 40 in3 41 v dd 42 i/o-a0/ck3 43 i/o-a2 44 i/o-a5 sp00624 pz3064 56-ball grid array a1 ball pad corner bottom view a b c d e f g h j k 10987654321 sp00674 pkg ball function a1 i/oa3 a2 i/oa5 a3 i/oa7 a4 v dd a5 i/od4 a6 in0/ck0 a7 gnd a8 i/od2 a9 i/od3 a10 i/od6 b1 i/oa4 b10 i/od7 c1 i/oa8 (tdi) c3 i/oa2 c4 i/oa0/ck3 c5 in3 c6 in1 c7 in2gtsn c8 i/od0 c10 i/od8 (tdo) pkg ball function d1 i/oa11 d3 i/oa12 d8 i/od11 d10 v dd e1 gnd e3 i/oa13 e8 i/od12 e10 i/od15 f1 i/oa15 f3 i/ob13 f8 i/od13 f10 i/oc15 (tck) g1 i/ob15 (tms) g3 i/ob11 g8 i/oc13 g10 gnd pkg ball function h1 v dd h3 i/ob3 h4 i/ob2 h5 v dd h6 i/oc2 h7 i/oc3 h8 i/oc4 h10 i/oc11 j1 i/ob10 j10 i/oc5 k1 i/ob8 k2 i/ob5 k3 i/ob4 k4 i/ob7 k5 i/ob0/ck2 k6 gnd k7 i/oc0/ck1 k8 i/oc10 k9 i/oc7 k10 i/oc8
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 15 pz3064 100-pin thin quad flat package pin function 1 i/o-a6 2 i/o-a7 3v dd 4 i/o-a8 (tdi) 5nc 6 i/o-a9 7nc 8 i/o-a10 9 i/o-a11 10 i/o-a12 11 gnd 12 i/o-a13 13 i/o-a14 14 i/o-a15 15 i/o-b15 (tms) 16 i/o-b14 17 i/o-b13 18 v dd 19 i/o-b12 20 i/o-b11 21 i/o-b10 22 nc 23 i/o-b9 24 nc 25 i/o-b8 26 gnd 27 nc 28 nc 29 i/o-b7 30 i/o-b6 31 i/o-b5 32 i/o-b4 pin function 33 i/o-b3 34 v dd 35 i/o-b2 36 i/o-b1 37 i/o-b0/ck2 38 gnd 39 v dd 40 i/o-c0/ck1 41 i/o-c1 42 i/o-c2 43 gnd 44 i/o-c3 45 i/o-c4 46 i/o-c5 47 i/o-c6 48 i/o-c7 49 nc 50 nc 51 v dd 52 i/o-c8 53 nc 54 i/o-c9 55 nc 56 i/o-c10 57 i/o-c11 58 i/o-c12 59 gnd 60 i/o-c13 61 i/o-c14 62 i/o-c15 (tck) 63 i/o-d15 64 i/o-d14 65 i/o-d13 66 v dd pin function 67 i/o-d12 68 i/o-d11 69 i/o-d10 70 nc 71 i/o-d9 72 nc 73 i/o-d8 (tdo) 74 gnd 75 i/o-d7 76 i/o-d6 77 nc 78 nc 79 i/o-d5 80 i/o-d4 81 i/o-d3 82 v dd 83 i/o-d2 84 i/o-d1 85 i/o-d0 86 gnd 87 in0/ck0 88 in2-gtsn 89 in1 90 in3 91 v dd 92 i/o-a0/ck3 93 i/o-a1 94 i/o-a2 95 gnd 96 i/o-a3 97 i/o-a4 98 i/o-a5 99 nc 100 nc sp00556 tqfp 100 76 1 25 75 51 26 50 package thermal characteristics philips semiconductors uses the temperature sensitive parameter (tsp) method to test thermal resistance. this method meets mil-std-883c method 1012.1 and is described in philips 1995 ic package databook . thermal resistance varies slightly as a function of input power. as input power increases, thermal resistance changes approximately 5% for a 100% change in power. figure 7 is a derating curve for the change in q ja with airflow based on wind tunnel measurements. it should be noted that the wind flow dynamics are more complex and turbulent in actual applications than in a wind tunnel. also, the test boards used in the wind tunnel contribute significantly to forced convection heat transfer, and may not be similar to the actual circuit board, especially in size. package q ja 44-pin plcc 44.9 c/w 44-pin tqfp 60.8 c/w 56-ball lfbga 65 c/w 100-pin tqfp 47.4 c/w 0 10 20 30 40 50 01234 5 percentage reduction in q ja (%) air flow (m/s) plcc/ qfp sp00419a figure 7. average effect of airflow on q ja
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 16 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 17 tqfp44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm sot376-1
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 18 lfbga56: low profile fine-pitch ball grid array package; 56 balls; body 6 x 6 x 1.05 mm sot516-1
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 19 tqfp100: plastic thin quad flat package; 100 leads; body 14 x 14 x 1.0 mm sot386-1
philips semiconductors product specification pz3064a/pz3064d 64 macrocell cpld with enhanced clocking 1999 jun 16 20 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1999 all rights reserved. printed in u.s.a. date of release: 06-99 document order number: 939775006115
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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